The present invention relates to signal transfer wirings formed on a semiconductor integrated device and, more specifically, to a high-speed, signal transfer method.
Recent emphasis has been towards increasing the density of semiconductor integrated circuit chips further, as well as increasing the areas of these chips. Accordingly, amounts of signal transmission lines used to connect logic circuits employed in the semiconductor integrated circuit are increased. In other words, the lengths of the signal wirings are increased. In addition to realizing such high integrating density and large areas, a line resistance associated with a wiring of a semiconductor integrated circuit is considerably increased since the widths of wirings are made narrower so as to achieve high integration. As a result, delay time caused by line resistance (simply referred to a "line resistance delay") is considerably increased, and thus this line resistance delay would occupy a substantial portion of signal propagation delay among the logic circuits. It is a major factor for increasing operation speeds of semiconductor integrated circuit devices to shorten such a line resistance delay.
As the signal transmission line for the conventional semiconductor integrated circuit, there are known a transmission scheme with an open-ended terminal, and a transmission scheme with a shortened terminal. For the signal wiring between the logic circuits, the open-ended terminal type transmission scheme has been widely employed in which no signal voltage drop caused by the line resistance appears, as represented in an equivalent circuit of FIG. 12. In this circuit, reference numerals 101 and 10b indicate logic circuits, namely reference numeral 101 is a driving circuit, and reference numeral 10b is a receiver circuit. Generally speaking, an emitter coupled logic circuit, so-called as an "ECL", in which bipolar transistors are employed as the driver circuit 101 and the receiver circuit 10b, and a CMOS circuit in which MOS transistors are employed as the driver circuit 101 and the receiver circuit 10b, have been widely utilized. In any of these circuits, the driving circuit 101 may be expressed by an equivalent voltage source 106 and an output resistor 105, and the output impedance of this circuit is several tens of ohms. The input impedance of the receiver circuit 10b is higher than several hundreds of Kilohms in the emitter coupled logic circuit where the input impedance is defined as the base input, whereas the input impedance of the CMOS logic circuit is the infinite, which is extremely large as compared with the wiring resistance. Thus, the driver circuit and the receiving circuit will actually constitute the open-ended terminal type transmission scheme.
In general, in such a transmission scheme in which wiring formed on an LSI (large-scale integration) has a line resistance which is relatively high, namely a distributed constant line (signal path) constructed of RC (resistors and capacitors), the rising time of a current waveform appearing at a line terminal when the line terminal is short-circuited is theoretically faster than the rising time of a voltage waveform appearing at the line terminal when the line terminal is open. This current waveform is called "Thomson's current curve", a detailed analysis of which is described in, for instance, Japanese publication entitled "Electric Circuit (2) in College Course" published by Ohm-Sha publisher, issued on May 30, 1969. This article describes such a case in which a DC voltage is applied to the limited length line, namely, it analyzes a case in which a limited length line is driven by an ideal voltage source.
Generally, when a transmission scheme with a shortened terminal is realized by employing the above-described ECL, an amplitude of a signal voltage appearing at the line terminal would be considerably lowered due to line resistance, as compared with that appearing at the source terminal. As a consequence, in a transmission scheme such, as shown in FIG. 13, the driver circuit is constituted by the current driver circuit and the receiver circuit is constituted by the current sensing circuit, as described in JP-A-2-265093. This drawing schematically represents a portion of the signal wirings of the sensing circuit for deriving the information stored in the memory cell. Reference numeral 1301 indicates a memory cell, and becomes a current driver circuit for supplying a read current Ir in correspondence with current supply capabilities of an MOS transistor 1308 in response to the information of the memory cell. At this time, since the MOS transistor 1308 is operated as the current source, the output resistance becomes substantially infinite. Reference numerals 1302 and 1303 denote signal wirings, reference numeral 1305 represents transistors functioning as terminal resistors, and reference numeral 1306 shows a current sensing circuit for converting the read current Ir into a corresponding voltage effected by the read current which flows through the resistor 1307. It should be noted that symbol "C" indicates a line capacitance per unit length, and symbol "R" shows a line resistance per unit length. Further, another conventional transmission scheme with a terminated receiving end is disclosed in JP-A-4-207226. Also, in this prior art system, the driver circuit is the current source, and thus the output resistance is considerably high.